? semiconductor components industries, llc, 2000 may, 2000 rev. 2 1 publication order number: mcr8dsm/d
preferred device
reverse blocking thyristors designed for high volume, low cost, industrial and consumer applications such as motor control; process control; temperature, light and speed control. ? small size ? passivated die for reliability and uniformity ? low level triggering and holding characteristics ? available in two package styles surface mount lead form e case 369a miniature plastic package e straight leads e case 369 ? device marking: device type, e.g., for mcr8dsm: cr8dsm, date code maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit peak repetitive offstate voltage (1) (t j = 40 to 110 c, sine wave, 50 to 60 hz, gate open) mcr8dsm mcr8dsn v drm, v rrm 600 800 volts onstate rms current (180 conduction angles; t c = 90 c) i t(rms) 8.0 amps average onstate current (180 conduction angles; t c = 90 c) i t(av) 5.1 amps peak non-repetitive surge current (1/2 cycle, sine wave, 60 hz, t j = 110 c) i tsm 90 amps circuit fusing consideration (t = 8.3 msec) i 2 t 34 a 2 sec forward peak gate power (pulse width 10 sec, t c = 90 c) p gm 5.0 watts forward average gate power (t = 8.3 msec, t c = 90 c) p g(av) 0.5 watt forward peak gate current (pulse width 10 sec, t c = 90 c) i gm 2.0 amps operating junction temperature range t j 40 to 110 c storage temperature range t stg 40 to 150 c (1) v drm and v rrm for all types can be applied on a continuous basis. ratings apply for negative gate voltage; positive gate voltage shall not be applied concurrent with negative potential on the anode. blocking voltages shall not be tested with a constant current source such that the voltage ratings of the device are exceeded. scrs 8 amperes rms 600 thru 800 volts preferred devices are recommended choices for future use and best overall value. device package shipping ordering information mcr8dsmt4 dpak 369a 16mm tape and reel (2.5k/reel) http://onsemi.com k g a dpak case 369a style 4 1 2 3 4 pin assignment 1 2 3 anode gate cathode 4 anode mcr8dsnt4 dpak 369a 16mm tape and reel (2.5k/reel)
mcr8dsm, mcr8dsn http://onsemi.com 2 thermal characteristics characteristic symbol max unit thermal resistance e junction to case thermal resistance e junction to ambient thermal resistance e junction to ambient (1) r jc r ja r ja 2.2 88 80 c/w maximum lead temperature for soldering purposes 1/8 from case for 10 seconds t l 260 c electrical characteristics (t j = 25 c unless otherwise noted) characteristics symbol min typ max unit off characteristics peak repetitive forward or reverse blocking current (v ak = rated v drm or v rrm ; r gk = 1.0 k ) (2) t j = 25 c t j = 110 c i drm i rrm e e e e 10 500 a on characteristics peak reverse gate blocking voltage (i gr = 10 a) v grm 10 12.5 18 volts peak reverse gate blocking current (v gr = 10 v) i rgm e e 1.2 a peak forward onstate voltage (3) (i tm = 16 a) v tm e 1.4 1.8 volts gate trigger current (continuous dc) (4) (v d = 12 v, r l = 100 )t j = 25 c t j = 40 c i gt 5.0 e 12 e 200 300 a gate trigger voltage (continuous dc) (4) (v d = 12 v, r l = 100 )t j = 25 c t j = 40 c t j = 110 c v gt 0.45 e 0.2 0.65 e e 1.0 1.5 e volts holding current (v d = 12 v, initiating current = 200 ma, gate open) t j = 25 c t j = 40 c i h 0.5 e 1.0 e 6.0 10 ma latching current (v d = 12 v, i g = 2.0 ma) t j = 25 c t j = 40 c i l 0.5 e 1.0 e 6.0 10 ma total turnon time (source voltage = 12 v, r s = 6.0 k , i t = 16 a(pk), r gk = 1.0 k ) (v d = rated v drm , rise time = 20 ns, pulse width = 10 s) tgt e 2.0 5.0 s dynamic characteristics characteristics symbol min typ max unit critical rate of rise of offstate voltage (v d = 0.67 x rated v drm , exponential waveform, r gk = 1.0 k , t j = 110 c) dv/dt 2.0 10 e v/ s (1) surface mounted on minimum recommended pad size. (2) ratings apply for negative gate voltage or r gk = 1.0 k . devices shall not have a positive gate voltage concurrently with a negative voltage on the anode. devices should not be tested with a constant current source for forward and reverse blocking capability such that the voltage applied exceeds the rated blocking voltage. (3) pulse test; pulse width 2.0 msec, duty cycle 2%. (4) r gk current not included in measurements.
mcr8dsm, mcr8dsn http://onsemi.com 3 + current + voltage v tm i drm at v drm i h symbol parameter v drm peak repetitive off state forward voltage i drm peak forward blocking current v rrm peak repetitive off state reverse voltage i rrm peak reverse blocking current v tm peak on state voltage i h holding current voltage current characteristic of scr anode + on state reverse blocking region (off state) reverse avalanche region anode forward blocking region i rrm at v rrm (off state) figure 1. average current derating figure 2. onstate power dissipation 6.0 0 i t(av) , average onstate current (amps) 110 105 100 i t(av) , average onstate current (amps) 3.0 6.0 0 8.0 4.0 2.0 0 t c , maximum allowable case temperature ( c) p 95 85 1.0 2.0 3.0 1.0 2.0 6.0 10 12 , average power dissipation (watts) (av) dc 180 120 90 60 = 30 dc 180 120 90 60 = 30 5.0 4.0 5.0 90 4.0 = conduction angle = conduction angle
mcr8dsm, mcr8dsn http://onsemi.com 4 figure 3. onstate characteristics figure 4. transient thermal response figure 5. typical gate trigger current versus junction temperature figure 6. typical gate trigger voltage versus junction temperature 5.0 0 v t , instantaneous onstate voltage (volts) 100 10 1.0 0.1 t, time (ms) 1.0 0.1 1.0 0.1 0.01 4.0 25 20 40 t j , junction temperature ( c) 1000 10 t j , junction temperature ( c) 25 65 40 0.1 20 5.0 i r (t) , transient thermal resistance 1.0 3.0 10 100 1000 10 k , gate trigger current ( a) i gt 50 110 65 5.0 110 35 50 v gt , gate trigger voltage (volts) , instantaneous onstate current (amps) t 80 typical @ t j = 25 c maximum @ t j = 25 c maximum @ t j = 110 c z jc(t) = r jc(t) r(t) 1.0 1.0 2.0 10 35 95 100 10 95 80 (normalized) gate open r gk = 1.0 k figure 7. typical holding current versus junction temperature figure 8. typical latching current versus junction temperature 65 110 40 t j , junction temperature ( c) t j , junction temperature ( c) i h , holding current (ma) i 1.0 0.1 25 5.0 20 50 95 , latching current (ma) l 10 10 35 80 r gk = 1.0 k 65 110 40 1.0 0.1 25 5.0 20 50 95 10 10 35 80 r gk = 1.0 k
mcr8dsm, mcr8dsn http://onsemi.com 5 figure 9. holding current versus gatecathode resistance 1000 10 k 100 r gk , gatecathode resistance (ohms) 10 6.0 4.0 2.0 0 i t j = 25 c figure 10. exponential static dv/dt versus gatecathode resistance and junction temperature 100 r gk , gatecathode resistance (ohms) 1000 10 1.0 static dv/dt (v/ s) t j = 110 c 1000 i gt = 10 a figure 11. exponential static dv/dt versus gatecathode resistance and peak voltage static dv/dt (v/ s) figure 12. exponential static dv/dt versus gatecathode resistance and gate trigger current sensitivity 8.0 i gt = 25 a , holding current (ma) h 100 90 c 70 c 100 r gk , gatecathode resistance (ohms) 1000 10 1.0 t j = 110 c 1000 100 v pk = 800 v 600 v 400 v 100 r gk , gatecathode resistance (ohms) 1000 10 1.0 v d = 800 v t j = 110 c 1000 100 i gt = 10 a static dv/dt (v/ s) i gt = 25 a
mcr8dsm, mcr8dsn http://onsemi.com 6 minimum recommended footprint for surface mounted applications surface mount board layout is a critical portion of the total design. the footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. with the correct pad geometry, the packages will self align when subjected to a solder reflow process. dpak 0.190 4.826 0.100 2.54 0.063 1.6 0.165 4.191 0.118 3.0 0.243 6.172 mm inches
mcr8dsm, mcr8dsn http://onsemi.com 7 package dimensions dpak case 369a13 issue z d a k b r v s f l g 2 pl m 0.13 (0.005) t e c u j h t seating plane z dim min max min max millimeters inches a 0.235 0.250 5.97 6.35 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.033 0.040 0.84 1.01 f 0.037 0.047 0.94 1.19 g 0.180 bsc 4.58 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.102 0.114 2.60 2.89 l 0.090 bsc 2.29 bsc r 0.175 0.215 4.45 5.46 s 0.020 0.050 0.51 1.27 u 0.020 0.51 v 0.030 0.050 0.77 1.27 z 0.138 3.51 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 123 4 style 4: pin 1. cathode 2. anode 3. gate 4. anode
mcr8dsm, mcr8dsn http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent r ights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into t he body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402745 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mcr8dsm/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (mf 1:00pm to 5:00pm munich time) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (mf 1:00pm to 5:00pm toulouse time) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (mf 12:00pm to 5:00pm uk time) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, england, ireland
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